The present invention relates to information processing systems in which multiple processing devices are coupled to a main storage memory and to auxiliary storage devices, e.g. disk drives. More particularly, the invention relates to information in the main storage memory and in the processing devices, used to associate virtual addresses with real addresses in main storage, and to a system for maintaining the coherency of such information in main storage and in the processing devices.
Among the recent trends in data processing are computer architectures which increasingly employ multiple processing devices that share a common interface to a main storage memory and to disk drives or other auxiliary storage devices. To enhance system performance, the processing devices can be equipped to store some of the data found in main storage memory. For example, cache memories can be provided, one within and uniquely associated with each of the processing devices and containing some of the information stored in main memory. Whenever one of the processing devices performs a data store or fetch operation in its cache memory rather than in the shared main memory, memory access time is substantially reduced.
In networks incorporating auxiliary storage devices, storage locations in such devices are identified with virtual addresses. While data is in main storage, its virtual address is associated or coupled with one of the real addresses in main storage. Each real address identifies a page frame or other separately identifiable unit of data within the main storage memory. This arrangement gives rise to the need to translate address data, i.e. correctly associate a virtual address with the corresponding real address in main memory. To this end, information systems can incorporate into the main memory an index or table to associate each virtual address with one of the real addresses (i.e. one of the page frames) in the main memory. Such table, known as a "primary directory", comprises a plurality of chains of primary directory entries, each entry associated with a different real address.
It is advantageous to provide in each of the processing devices a "secondary directory" whereby some of the primary mapping information in main storage is also resident in each processing device. The secondary directories provide fast lookup tables for performing address translations without the need to gain access to the primary directory. Thus, primary directory access time is substantially reduced, improving network performance. Primary directory translates or searches are initiated with hardware logic in each of the processing devices only when the respective secondary directory lacks the information necessary for the operation.
This advantage, however, depends on the ability to maintain coherency of the secondary directories and the primary directory, i.e. keeping the secondary directories current with updates to the primary directory. It is known to achieve coherency with a quiesce, generally as follows:
1. one of the processing devices is to modify the primary directory;
2. the modifying processor sends the appropriate message to the remaining processing devices;
3. the remaining processing devices receive the message and confirm to the sending processing device that they have received the message;
4. the sending processor modifies the primary directory, while the remaining processors are kept inactive;
5. the modifying processor sends a message to the remaining processors that the primary directory update is complete; and
6. the other processors respond to the message and resume normal operation.
The quiesce is time consuming but heretofore considered necessary. Without it, one processor might perform a primary directory translate while another processor is updating the primary directory. One processor might store data from a page frame into its secondary directory, while another processor is invalidating the same page in the primary directory. One processor might be updating the primary directory to indicate that the associated data has been modified, at the same time another processor resets a reference bit associated with the same data. The result would be a failure to update the corresponding data as stored on an auxiliary storage device.
Therefore, it is an object of the present invention to provide a multiprocessor network in which data translations can be temporarily inhibited during updates to a primary directory, without a quiesce.
Another object is to maintain directory coherency without unnecessary secondary directory purges in such a network by ensuring, temporarily, that no primary directory translations can occur which might raise the need for a purge.
A further object is to provide a network in which primary directory entries can be removed from the primary directory at a time when no hardware translations are in progress.
Yet another object is to provide a means of updating status bits in a primary directory atomically with respect to hardware primary directory translations.